1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Background Art
In recent years, multilayer interconnects of semiconductor devices have been required to provide high integration density and low resistance. Conventionally, Al (aluminum) line layers have been frequently adopted as line layers of semiconductor devices. However, in recent years, a growing number of Cu (copper) line layers have become adopted as line layers of semiconductor devices, to improve margins for fabrication of lines and to further lower the resistance of lines.
In this case, a combination of a Cu line layer and an Al via plug layer is considered to be effective in terms of cost reductions. However, the combination of a Cu line layer and an Al via plug layer has problems as described below.
First, there is a problem concerning barrier break of a barrier metal layer formed between a Cu line layer and an Al via plug layer by sputtering. In other words, there is a problem that a barrier metal layer is not correctly formed by sputtering in some cases. This barrier break tends to occur in the vicinity of the edge between the bottom surface and the side surface of a via hole, and particularly in a peripheral portion of a wafer. This is because, in general, the coverage of a barrier metal layer is bad in the vicinity of the edge of a via hole. If the barrier break occurs in a case that the combination of a Cu line layer and an Al via plug layer is adopted, Cu in the Cu line layer diffuses into the Al via plug layer. If such diffusion occurs, voids occur in the Cu line layer and a disconnection occurs between the Cu line layer and the Al via plug layer.
Second, unburying (unfilling) of the Al via plug layer is a problem. Unburying of the Al via plug layer tends to occur when the aspect ratio of a via hole increases.
It is difficult to prevent the barrier break and the unburying at the same time. The barrier break can be prevented by increasing the thickness of the barrier metal layer. However, if the thickness of the barrier metal layer is increased, the amount of an overhang of the barrier metal layer at the opening of the via plug increases, and the unburying of the Al via plug layer tends to occur. On the contrary, if the thickness of the barrier metal layer is decreased, the coverage in the vicinity of the edge of a via hole becomes worse, and the barrier break tends to occur. If the aspect ratio of a via hole becomes larger than 2, it becomes very difficult to prevent the barrier break and the unburying at the same time. For example, when the height of the via hole is 300 nm, it becomes very difficult to prevent the barrier break and the unburying at the same time in a case that the diameter of the via hole becomes larger than 150 nm.
JP-A 2006-253666 (KOKAI) discloses a semiconductor device including a Cu line layer and a Cu via plug layer between which a CoWP cap metal layer, a cap metal nitride layer, and a barrier metal layer containing Ta are provided. JP-A 2007-42662 (KOKAI) discloses a semiconductor device including a Cu line layer and an Al via plug layer between which a barrier metal layer containing Ti is provided.